View AD9824-15_8359474.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9824 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 complete 14-bit 30 msps ccd signal processor functional block diagram dataclk shd shp 2:1 mux dout aux2in clpdm ccdin aux1in internal timing 2db~36db avdd dvdd dvss avss drvdd drvss 10 8 digital interface sdata sck sl cds vga buf 2:1 mux clp ad9824 clp adc 4db 6db color steering hd vd pxga 6 band gap reference vrt vrb clp 14 blk clamp level control registers clpob pblk features 14-bit 30 msps a/d converter 30 msps correlated double sampler (cds) 4 db 6 db 6-bit pixel gain ampli?er ( pxga ? ) 2 db to 36 db 10-bit variable gain ampli?er (vga) low noise clamp circuits analog preblanking function auxiliary inputs with vga and input clamp 3-wire serial digital interface 3 v single-supply operation low power: 153 mw @ 3 v supply space-saving 48-lead lfcsp package applications high performance digital still cameras industrial/scientific imaging product description the ad9824 is a complete analog signal processor for ccd applications. it features a 30 mhz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan area ccd arrays. the ad9824? signal chain consists of an input clamp, a corre lated double sampler (cds), pxga , a digitally controlled vga, a black level clamp, and a 14-bit a/d converter. additional input modes are also pro- vided for processing analog video signals. the internal registers are programmed through a 3-wire serial digital interface. programmable features include gain adjustment, black level adjustment, input con?uration, and power-down modes. the ad9824 operates from a single 3 v power supply, typically dissipates 153 mw, and is packaged in a 48-lead lfcsp. pxga is a registered trademark of analog devices, inc.
rev. 0 ?2? ad9824especifications general specifications parameter min typ max unit temperature range operating e20 +85
rev. 0 ?3? ad9824 parameter min typ max unit notes p ower consumption 153 mw see tpc 1 for power curves maximum clock rate 30 mhz cds gain 0 db allowable ccd reset transient 1 500 mv see input waveform in footnote 1 max input range before saturation 1 1.0 v p-p pxga gain at 4 db max ccd black pixel amplitude 1 200 mv pixel gain amplifier ( pxga ) max input range 1.0 v p-p max output range 1.6 v p-p gain control resolution 64 steps gain monotonicity guaranteed gain range (two?s complement coding) see figure 28 for pxga gain curve min gain ( pxga gain code 32) e2.5 db max gain ( pxga gain code 31) 9.5 db variable gain amplifier (vga) max input range 1.6 v p-p max output range 2.0 v p-p gain control resolution 1024 steps gain monotonicity guaranteed gain range see figure 29 for vga gain curve low gain (vga gain code 77) 2 db max gain (vga gain code 1023) 36 db black level clamp clamp level resolution 256 steps clamp level measured at adc output min clamp level 0 lsb max clamp level 1020 lsb system performance specitcations include entire signal chain gain accuracy 2 gain = (0.0353
rev. 0 ?4? ad9824especifications aux1-mode specifications parameter min typ max unit power consumption 120 mw maximum clock rate 30 mhz input buffer gain 0db max input range 1.0 v p-p vga max output range 2.0 v p-p gain control resolution 1023 steps gain (selected using vga gain register) min gain 0 db max gain 36 db specitcations subject to change without notice. aux2-mode specifications parameter min typ max unit power consumption 120 mw maximum clock rate 30 mhz input buffer (same as aux1-mode) vga max output range 2.0 v p-p gain control resolution 512 steps gain (selected using vga gain register) min gain 0 db max gain 18 db active clamp clamp level resolution 256 steps clamp level (measured at adc output) min clamp level 0 lsb max clamp level 1020 lsb specitcations subject to change without notice. (t min to t max , avdd = dvdd = 3.0 v, f dataclk = 30 mhz, unless otherwise noted.) (t min to t max , avdd = dvdd = 3.0 v, f dataclk = 30 mhz, unless otherwise noted.)
rev. 0 ad9824 ?5? absolute maximum ratings with respect parameter to min max unit avdd1, avdd2 avss e0.3 +3.9 v dvdd1, dvdd2 dvss e0.3 +3.9 v drvdd drvss e0.3 +3.9 v digital outputs drvss e0.3 drvdd + 0.3 v s hp, shd, dataclk dvss e0.3 dvdd + 0.3 v clpob, clpdm, pblk dvss e0.3 dvdd + 0.3 v sck, sl, sdata dvss e0.3 dvdd + 0.3 v vrt, vrb, cmlevel avss e0.3 a vdd + 0.3 v byp1-3, ccdin avss e0.3 avdd + 0.3 v junction temperature 150
rev. 0 ad9824 ?6? pin function descriptions pin number name type description 1e12 d2ed13 do digital data outputs. pin 12 (d13) is msb. 13 drvdd p digital output driver supply 14 drvss p digital output driver ground 15, 41 dvss p digital ground 16 dataclk di digital data output latch clock 17 dvdd1 p digital supply 1 18 hd di horizontal drive. used with vd for color steering control. 19 pblk di preblanking clock input 20 clpob di black level clamp clock input 21 shp di cds sampling clock for ccd?s reference level 22 shd di cds sampling clock for ccd?s data level 23 clpdm di input clamp clock input 24 vd di vertical drive. used with hd for color steering control. 25, 26, 35 avss p analog ground 27 avdd1 p analog supply 1 28 byp1 ao internal bias level decoupling 29 byp2 ao internal bias level decoupling 30 ccdin ai analog input for ccd signal 31 nc nc internally not connected 32 byp3 ao internal bias level decoupling 33 avdd2 p analog supply 2 34 aux2in ai analog input 36 aux1in ai analog input 37 nc nc internally not connected 38 vrt ao a/d converter top reference voltage decoupling 39 vrb ao a/d converter bottom reference voltage decoupling 40 dvdd2 p digital supply 2 42 nc nc internally not connected 43 stby di standby mode, active high. same as total power-down mode. 44 sl di serial digital interface load pulse 45 sdata di serial digital interface data 46 sck di serial digital interface clock 47, 48 d0ed1 di digital data outputs. pin 47 (d0) is lsb. type: ai = analog input, ao = analog output, di = digital input, do = digital output, p = power pin configurations 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) aux1in avss aux2in avdd2 byp3 nc ccdin d2 d3 d4 d5 d6 d7 d8 nc = no connect d9 d10 d11 d12 byp2 byp1 avdd1 avss ad9824 ( msb) d13 avss d1 d0 (lsb) sck sdata sl stby nc dvss dvdd2 vrb vrt nc drvdd drvss dvss dataclk dvdd1 hd pblk clpob shp shd clpdm vd
rev. 0 ad9824 ?7? definitions of specifications differential nonlinearity (dnl) an ideal adc exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. thus, every code must have a tnite width. no missing codes guaranteed to 14-bit resolution indicates that all 16,384 codes, respectively, must be present over all operating conditions. peak nonlinearity peak nonlinearity, a full signal chain specitcation, refers to the peak deviation of the output of the ad9824 from a true straight line. the point used as zero scale occurs 1/2 lsb before the t rst code transition. p ositive full scale is detned as a level 1, 1/2 lsb beyond the last code transition. the deviation is measured fr om the middle of each particular output code to the true straight l ine. the error is then expressed as a percentage of the 2 v adc full-scale signal. the input signal is always appropriately gained up to tll the adc?s full-scale range. total output noise the rms output noise is measured using histogram techniques. the standard deviation of the adc output codes is calculated in lsb and represents the rms noise level of the total signal chain at the specited gain setting. the output noise can be converted to an equivalent voltage using the relationship 1 lsb = (adc full scale/2 n codes) where n is the bit resolution of the adc. for the ad9824, 1 lsb is 125
rev. 0 ad9824 ?8? etypical performance characteristics sample rate e mhz 180 140 100 10 30 20 power dissipation e mw 110 130 150 170 160 120 v dd = 2.7v v dd = 3.0v v dd = 3.3v 190 tpc 1. power vs. sample rate 0.5 0 0 e0.25 0.25 e0.5 4000 2000 6000 8000 10000 12000 14000 16000 tpc 2. typical dnl performance vga gain code e lsb 100 0 0 1023 511 output noise e lsb 255 10 60 767 90 80 70 50 40 30 20 tpc 3. output noise vs. vga gain
rev. 0 ad9824 ?9? ccd mode and aux mode timing n n+1 n+2 n+9 n+10 t id t id t s1 t s2 t cp t inh t od t h ne10 ne9 ne8 ne1 n notes 1. recommended placement for dataclk rising edge is between the shd rising edge and next shp falling edge. 2. ccd signal is sampled at shp and shd rising edges. shp shd dataclk output data ccd signal figure 5. ccd mode timing ccd signal effective pixels clpob clpdm optical black pixels horizontal blanking dummy pixels effective pixels pblk notes 1. clpob and clpdm will overwrite pblk. pblk will not affect clamp operation if overlapping clpdm and/or clpob. 2. pblk signal is optional. 3. digital output data will be all zeros during pblk. output data latency is 9 dataclk cycles. output data effective pixel data ob pixel data dummy black effective data figure 6. typical ccd mode line clamp timing dataclk output data video signal n n+1 n+2 n+8 n+9 ne10 ne9 ne8 ne1 n t id t cp t od t h figure 7. aux mode timing
rev. 0 ad9824 ?10? pixel gain amplifier ( pxga ) timing frame n line 0 line 1 line 2 line m 0101... 2323... 0101... line me1 line 0 line 1 line 2 line m 0101... 2323... 0101... line me1 * 0 = gain0, 1 = gain1, 2 = gain2, 3 = gain3 frame n+1 vd hd figure 8. pxga mode 1 (mosaic separate) frame/line gain register sequence shp hd 3ns min 3ns min pxga gain gain0 gain1 gain0 gain3 gain2 gainx gainx vd notes 1. minimum pulsewidth for hd and vd is 5 pixel cycles. 2. both vd and hd are internally updated at shp rising edges. minimum setup time is 3 ns. 3. every hd rising edge with a previous vd rising edge will reset to 0101. 4. every hd rising edge without a previous vd rising edge will alternate between 0101... and 2323. 5 pixel min figure 9. pxga mode 1 (mosaic separate) detailed timing 0101... 2323... 0101... 0101... 2323... 0101... hd line 0 line 1 line 2 line m line me1 line 0 line 1 line 2 line m line me1 even field odd field * 0 = gain0, 1 = gain1, 2 = gain2, 3 = gain3 vd figure 10. pxga mode 2 (interlace) frame/line gain register sequence shp hd pxga gain gain0 gain1 gain0 gain3 gain2 gainx gainx 3ns min 3ns min 5 pixel min vd notes 1. both vd and hd are internally updated at shp rising edges. 2. every hd rising edge with a previous vd rising or falling edge will reset to 0101. 3. every hd rising edge without a previous vd rising edge will alternate between 0101... and 2323. figure 11. pxga mode 2 (interlace) detailed timing
rev. 0 ad9824 ?11? hd * 0 = gain0, 1 = gain1, 2 = gain2 012012012... 012012012... ...01201 vd line n line n+1 figure 12. pxga mode 3 (3-color) frame/line gain register sequence shp hd 5 pixel min pxga gain gain1 vd gain2 gain0 gain1 gain0 gainx gain0 gainx 3ns min 5 pixel min notes 1. both vd and hd are internally updated at shp rising edges. 2. every hd rising edge with a previous vd rising edge will reset to 012012. figure 13. pxga mode 3 (3-color) detailed timing vd hd * 0 = gain0, 1 = gain1, 2 = gain2, 3 = gain3 line n line n+1 012301230123... ...01230 01230123012... figure 14. pxga mode 4 (4-color) frame/line gain register sequence shp hd 5 pixel min pxga gain gain1 vd gain2 gain0 gain1 gain0 gainx gain0 gainx 3ns min 5 pixel min notes 1. both vd and hd are internally updated at shp rising edges. 2. every hd rising edge with a previous vd rising edge will reset to 01230123. figure 15. pxga mode 4 (4-color) detailed timing
rev. 0 ad9824 ?12? 0101... 0101... 0101... * 0 = gain0, 1 = gain1, 2 = gain2, 3 = gain3 2323... 2323... 2323... hd line 0 line 1 line 2 line m line me1 line 0 line 1 line 2 line m line me1 even field odd field vd figure 16. pxga mode 5 (vd selected) frame/line gain register sequence shp hd 5 pixel min pxga gain gain0 gain1 gain0 notes 1. both vd and hd are internally updated at shp rising edges. 2. every hd rising edge with a previous vd falling edge will reset to 0101. 3. every hd rising edge with a previous vd rising edge will reset to 2323. 4. every hd rising edge without a previous vd rising edge will repeat either 0101... (even) or 2323... (odd). gain3 gain2 gainx gainx 3ns min vd 3ns min figure 17. pxga mode 5 (vd selected) detailed timing frame n vd line 0 line 1 line 2 line m 0101... 1212... 0101... line me1 line 0 line 1 line 2 line m 0101... 1212... 0101... line me1 * 0 = gain0, 1 = gain1, 2 = gain2 frame n+1 hd figure 18. pxga mode 6 (mosaic repeat) frame/line gain register sequence shp hd pxga gain gain0 gain1 gain0 notes 1. minimum pulsewidth for hd and vd is 5 pixel cycles. 2. both vd and hd are internally updated at shp rising edges. minimum setup time is 3 ns. 3. every hd rising edge with a previous vd rising edge will reset to 0101. 4. every hd rising edge without a previous vd rising edge will alternate between 0101... and 1212. gain2 gainx gainx gain1 3ns min vd 3ns min 5 pixel min figure 19. pxga mode 6 (mosaic repeat) detailed timing
rev. 0 ad9824 ?13? shp hd 3ns min gain1 vd gain0 gain2 gain3 3ns min 1. both vd and hd are internally updated at shp rising edges. 2. vd = 0 and hd = 0 selects gain0. 3. vd = 0 and hd = 1 selects gain1. 4. vd = 1 and hd = 0 selects gain2. 5. vd = 1 and hd = 1 selects gain3. gain0 pxga gain notes figure 20. pxga mode 7 (user-speci?ed) detailed timing
rev. 0 ad9824 ?14? serial interface timing and internal register description table i. internal register map register address data bits name a0 a1 a2 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 operation 0 0 0 channel select power-down software ob clamp 0 1 1 2 0 1 0 1 0 1 ccd/aux1/2 modes reset on/off vga gain 1 0 0 lsb msb x clamp level 0 1 0 lsb msb x x x control 1 1 0 color steering mode pxga clock polarity select for 0 1 0 1 three- x selection on/off shp/shd/clp/data state pxga gain0 0 0 1 lsb msb x x x x x pxga gain1 1 0 1 lsb msb x x x x x pxga gain2 0 1 1 lsb msb x x x x x pxga gain3 1 1 1 lsb msb x x x x x notes 1 internal use only. must be set to zero. 2 must be set to one. sdata sck sl rnw test bit 0 a2 0 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 t ds t dh t ls t lh notes 1. sdata bits are internally latched on the rising edges of sck. 2. rnw = read-not-write. set low for write operation. 3. test bits = internal use only. must be set low. 4. system update of loaded registers occurs on sl rising edge. figure 21. serial write operation sdata sck sl rnw test bit 10 0 a0 a1 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 t ds t dh t ls t lh notes 1. rnw = read-not-write. set high for read operation. 2. test bits = internal use only. must be set low. 3. serial data from the selected register is valid starting after the 5th sck falling edge and is updated on sck falling edges. t dv figure 22. serial readback operation
rev. 0 ad9824 ?15? sdata sck sl a0 a1 a2 d0 d10 d0 d9 d0 d0 d7 rnw 0 0 d9 0 00 d0 1 21735 34 27 26 16 6 5 4 3 44 45 51 63 62 57 56 50 68 ... ... ... ... ... ... ... ... 10 bits acg gain d5 d0 d5 d0 d0 d5 d5 ... ... ... ... ... ... ... ... ... notes 1. any number of adjacent registers may be loaded sequentially, beginning with the lowest address and incrementing one address at a time. 2. when sequentially loading multiple registers, the exact register length (shown above) must be used for each register. 3. all loaded registers will be simultaneously updated with the rising edge of sl. 8 bits clamp level 10 bits control 11 bits operation 6 bits pxga gain0 6 bits pxga gain1 6 bits pxga gain2 6 bits pxga gain3 figure 23. continuous serial write operation to all registers sdata a0 a1 a2 d1 d0 d1 d2 d3 d4 d5 d0 d3 d2 d4 0 0 23 24 12 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 29 18 ... ... d5 0 01 d5 d5 d0 d0 rnw sck sl pxga gain0 pxga gain1 pxga gain3 pxga gain2 ... ... ... figure 24. continuous serial write operation to all pxga gain registers table ii. operation register contents (default value x000) optical black clamp reset power-down modes channel selection d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 1 0 1 0 1 1 2 0 1 0 enable clamping 0 normal 0 0 normal power 0 0 ccd mode 1 disable clamping 1 reset all registers 0 1 test only 0 1 aux1 mode to default 1 0 standby 1 0 aux2 mode 11 total power-down 11 test only notes 1 must be set to zero. 2 set to one. table iii. vga gain register contents (default value x000) msb lsb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gain (db) x0 0 010111112.0 ?? ?? ??
rev. 0 ad9824 ?16? table iv. clamp level register contents (default value x080) msb lsb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 clamp level (lsb) x xx 0000 0000 0 0000 0001 4 0000 0010 8 ?? ?? ?? pxga color steering modes d10 d9 d8 d7 d6 d5 d4 d3 2 d2 d1 d0 x0 enable 0 1 0 1 0r ising edge trigger 0 active low 0 active low 0 disable 0 0 0 steering disabled 1 three-state 1 falling edge trigger 1 active high 1 active high 1 enable 0 0 1 mosaic separate 010 interlace 011 3-color 100 4-color 101 vd selected 110 mosaic repeat 111 user specited notes 1 must be set to zero. 2 when d3 = 0 ( pxga disabled), the pxga gain is txed to code 63 (3.3db). table vi. pxga gain registers for gain0, gain1, gain2, gain3 (default value x000) msb lsb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 gain (db) * xxxxx 011111+9.5 ?? ?? ?? ?? ?? ??
rev. 0 ad9824 ?17? circuit description and operation the ad9824 signal processing chain is shown in figure 25. each processing step is essential in achieving a high quality image from the raw ccd pixel data. dc restore to reduce the large dc offset of the ccd output signal, a dc res tore circuit is used with an external 0.1 pxga the pxga provides separate gain adjustment for the individual color pixels. a programmable gain ampliter with four separate values, the pxga has the capability to multiplex its gain value on a pixel-to-pixel basis. this allows lower output color pixels to be gained up to match higher output color pixels. also, the pxga may be used to adjust the colors for white balance, reducing the a mount of digital processing that is needed. the four different gain values are switched according to the color steering circuitry. seven different color steering modes for different types of ccd c olor tlter arrays are programmed in the ad9824?s control regis- ter. for example, mosaic separate steering mode accommodates t he popular bayer arrangement of red, green, and blue tlters (see figure 26). 2db to 36db clpdm ccdin digital filtering clpob dc restore optical black clamp 0.1 f dout 14-bit adc vga 8-bit dac clamp level register 8 vga gain register 10 cds input offset clamp internal v ref 2v full scale color steering 4:1 mux 3 gain0 gain1 gain2 gain3 pxga e2db to +10db pxga mode selection 2 6 vd hd pxga gain registers 14 figure 25. ccd mode block diagram
rev. 0 ad9824 ?18? rr gb gb gr gr bb ccd: progressive bayer line0 gain0, gain1, gain0, gain1... rr gr gr gb gb bb line1 line2 gain2, gain3, gain2, gain3... gain0, gain1, gain0, gain1... mosaic separate color steering mode figure 26. ccd color filter example: progressive scan line0 gain0, gain1, gain0, gain1... rr gr gr line1 line2 gain0, gain1, gain0, gain1... gain0, gain1, gain0, gain1... gb gb bb line0 gain2, gain3, gain2, gain3... line1 line2 gain2, gain3, gain2, gain3... gain2, gain3, gain2, gain3... ccd: interlaced bayer even field vd selected color steering mode odd field gb gb bb gb gb bb gb gb bb rr gr gr rr gr gr rr gr gr figure 27. ccd color filter example: interlaced the same bayer pattern can also be interlaced, and the vd selected mode should be used with this type of ccd (see figure 27). the color steering performs the proper multiplexing of the r, g, and b gain values (loaded into the pxga gain regis- ters) and is synchronized by the user with vertical (vd) and horizontal (hd) sync pulses. for more detailed information, see the pxga timing section. the pxga gain for each of the four channels is variable from e2.5 db to +9.5 db, controlled in 64 steps t hrough the serial interface. the pxga gain curve is shown in f igure 28. pxga gain register code 10 32 pxga gain e db 40 48 58 0 8 16 24 31 6 4 2 0 e2 e4 8 (100000) (011111) figure 28. pxga gain curve variable gain ampliter the vga stage provides a gain range of 2 db to 36 db, pro gram- mable with 10-bit resolution through the serial digital interface. combined with approximately 4 db from the pxga stage, the total gain range for the ad9824 is 6 db to 40 db. the minimum gain of 6 db is needed to match -a 1 v input signal with the adc full-scale range of 2 v. when compared to 1 v fu ll-scale systems (such as adi?s ad9803 ), the equi valent gain range is 0 db to 34 db. t he vga gain curve follows a linear-in-db shape. the exact vga gain can be calculated for any gain register value by using the following equation: code range gain equation (db) 0e1023 gain = (0.0353)( code ) as shown in the ccd mode specitcations, only the vga gain range from 2 db to 36 db has tested and guaranteed accuracy. this corresponds to a vga gain code range of 77 to 1023. the gain accuracy specitcations also include a pxga gain of approxi- mately 3.3 db, for a total gain range of 6 db to 40 db. vga gain register code 36 0 vga gain e db 127 255 383 511 639 767 895 1023 30 24 18 12 6 0 figure 29. vga gain curve (gain from pxga not included) optical black clamp the optical black clamp loop is used to remove residual offsets in the signal chain and to track low frequency variations in the ccd?s black level. during the optical black (shielded) pixel interval on each line, the adc output is compared with a txed black level reference, selected by the user in the clamp level register. the clamp level is adjustable from 0 to 1020 lsb, in 256 steps. the resulting error signal is t ltered to reduce noise, and the correction va lue is app lied to the adc input through a d/a converter. normally, the optical black clamp loop is turned on once per horizontal line, but this loop can be updated more slowly to suit a particular application. if external digital clamping is us ed du rin g t he po st pr oce ssi ng, the ad9824 optical black clamping may be disabled using bit d5 in the operation register (see serial interface timing and internal register description section). when the loop is disabled, the clamp level register may still be used to provide programm able offset adjustment. horizontal timing is shown in figure 6. the clpob pulse should be placed during the ccd?s optical black pixels. it is recommended that the clpob pulse duration be at least 20 pixels wide to minimize clamp noise. shorter pulsewidths may be used, but clamp noise may increase and the ability to track low frequ ency variations in the black level will be reduced.
rev. 0 ad9824 ?19? a/d converter the ad9824 uses high performance adc architecture, opti- mized for high speed and low power. differential nonlinearity (dnl) performance is typically better than 0.5 lsb, as shown in tpc 2. instead of the 1 v full-scale range used by the earlier ad9801 and ad9803 products from analog devices, the ad9824?s adc uses a 2 v input range. better noise perfor- mance results from using a larger adc full-scale range (see tpc 3). aux1 mode for applications that do not require cds, the ad9824 can be configured to sample ac-coupled waveforms. figure 30 shows the circuit configuration for using the aux1 channel input (pin 36). a single 0.1
rev. 0 ad9824 ?20? ccd ccdin buffer v out 0.1 f ad9824 adc out register- data serial interface digital outputs digital image processing asic timing generator v-drive ccd timing cds/clamp timing figure 32. system applications diagram applications information the ad9824 is a complete analog front end (afe) product for digital still camera and camcorder applications. as shown in figure 32, the ccd image (pixel) data is buffered and sent to the ad9824 analog input through a series input capacitor. the ad9824 performs the dc restoration, cds, gain adjust- ment, black level correction, and analog-to-digital conversion. the ad9824?s digital output data is then processed by the image processing asic. the internal registers of the ad9824? used to control gain, offset level, and other functions?are programmed by the asic or microprocessor through a 3-wire serial digital interface. a system timing generator provides the clock signals for both the ccd and the afe.
rev. 0 ad9824 ?21? internal power-on reset circuitry after pow er-on, the ad9824 will automatically reset all internal registers and perform internal calibration procedures. this takes approximately 1 ms to complete. during this time, normal clock sig nals and serial write operations may occur. however, serial register writes will be ignored until the internal reset opera- tion is completed. grounding and decoupling recommendations as shown in figure 33, a single ground plane is recommended for the ad9824. this ground plane should be as continuous as possib le, particularly around pins 25 through 39. this will e nsure that all analog decoupling capacitors provide the lowest possible impedance path between the power and bypass pins and their respective ground pins. all decoupling capacit ors should be located as close as possible to the package pins. a single clean power supply is recommended for the ad9824, but a separate digital driver supply may be used for drvdd (pin 13). drvdd should always be decoupled to drvss (pin 14), which should be connected to the analog ground plane. a dvantages of using a separate digital driver supply include using a lower voltage (2.7 v) to match levels with a 2.7 v asic, and reducing digital po wer dissipation and potential noise coupling. if the d igital outputs (pins 1 e12) must drive a load larger than 20 pf, buff- e ri ng is recommended to reduce digital code transition noise. alternatively, placing series resistors close to the d igital out- put pins may also help reduce noise. 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 37 48 47 46 45 44 39 38 43 42 41 40 pin 1 identifier top view (not to scale) aux1in avss aux2in avdd2 byp3 nc ccdin byp2 byp1 avdd1 avss avss d2 d3 d4 d5 d6 d7 d8 d9 d10 ( msb) d13 ad9824 d1 d0 (lsb) sck sdata sl stby dvss dvdd2 vrb vrt nc drvdd drvss dvss dataclk dvdd1 hd pblk clpob shp shd clpdm vd 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f 3v analog supply ccd signal 3v analog supply 14 data outputs 3 serial interface 1.0 f 1.0 f 0.1 f 3v analog supply 8 clock inputs 0.1 f 0.1 f 3v analog supply 3v driver supply nc = no connect d11 d12 nc figure 33. recommended circuit configuration for ccd-mode
rev. 0 ad9824 ?22? outline dimensions dimensions shown in millimeters and (inches) 48-lead frame chip scale package lfcsp 7 x 7 mm body (cp-48) pin 1 indicator top view 6.75 (0.2657) bsc sq 7.00 (0.2756) bsc sq 1 48 1 2 13 37 36 24 25 bottom view 5.45 (0.2146) 5.30 (0.2087) sq 5.15 (0.2028) 0.60 (0.0236) 0.42 (0.0165) 0.24 (0.0094) 4 0.50 (0.0197) 0.40 (0.0157) 0.30 (0.0118) 0.30 (0.0118) 0.23 (0.0091) 0.18 (0.0071) 0.50 (0.0197) bsc 12 max 0.20 (0.0079) ref 0.70 (0.0315) max 0.65 (0.0276) nom 0.90 (0.0354) max 0.85 (0.0335) nom 0.05 (0.0020) 0.01 (0.0004) 0.00 (0.0000) 5.50 (0.2165) ref seating plane coplanarity controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards mo-220
?23?
?24? c02956?0?5/02(0) printed in u.s.a.

▲Up To Search▲

Price & Availability of AD9824-15

	To Download AD9824-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .